As known in the art, a plurality of integrated circuit (IC) die are formed on a semiconductor wafer by performing semiconductor processing including lithography, etch, ion implant and thin film processes. Following formation of the IC die, the wafer is sawed for singulation of the IC die. The vacant wafer spaces between the IC die used for sawing the wafer are referred to as scribe line areas.
To assess the electrical performance of the IC die, a predetermined pattern of measuring elements or test elements within a so-called test modules (TM) are generally formed in the scribe line areas of the wafer. The TMs generally include a plurality of discrete elements (e.g., MOS transistors, bipolar transistors, capacitors), sometimes interconnected as arrays of parallel elements, where the discrete elements correspond to discrete devices on the IC die. In order to secure yield at assembly test, the TM is electrically tested at wafer level, such as after an early metal level (e.g., first metal) and/or after completion of wafer processing, for determining whether the discrete circuit elements and components thereof are suitably formed (e.g., proper threshold voltage for MOS devices, Hfe for bipolar devices, I-V characteristics, and junction breakdown voltages) for the IC die. Conventional wafer level testing of TMs is performed by an automatic test system including a probe card and a test program that are both specific to the TM, along with a generic probe system and generic measurement/tester apparatus.
Wafer level testing on each active die generally requires significant engineering resources (e.g., 7 days minimum) and specific probe card hardware ranging in cost from about $2,000 to $10,000. To test the wafer, the specific wafer test cost can vary from $2 (sample probe) to >$200 per wafer. As a result of this cost, some IC products do not include any wafer level testing and thus rely solely on package level testing. Moreover, IC die for Wafer Scale Packaging (WSP) which involves a relayout process for the wafer at assembly, does not permit testing of the IC product before the last relayout is complete. Without wafer level testing or wafer level testing that can provide an accurate assessment of actual performance by the IC die, wafer fab induced yield problems may not be discovered for weeks or months after the wafer has completed its processing in the wafer fab. This long delay between wafer fab processing and testing can jeopardize deliveries to the customer and prevent prompt feedback to the wafer fab needed for timely process correction.